As integrated circuit devices become more highly integrated, the fabrication processes for the integrated circuits may become more complicated, and even more stringent process management may be required. These requirements may adversely impact manufacturing productivity and may lower manufacturing yields and reliability of the integrated circuit devices.
An area of increasing integration has been in integrated circuit memory devices. With each new generation of memory devices, more and more bits of data may be stored in a single integrated circuit. However, the increasing memory density may make it more difficult to maintain adequate process tolerances and alignment tolerances in the integrated circuit.
For example, Dynamic Random Access Memory (DRAM) devices that can store more than 16 MB of data in a single integrated circuit, often use three-dimensional capacitor structures to provide the requisite integration density. Capacitor-Over-Bitline (COB) cell structures is one example of a three-dimensional structure. In such a COB cell structure, it is important to insure that there are adequate spacing margins between a Direct Contact (DC) that connects a bit line to a source region of a transistor and a word line, and that there are adequate spacing margins between a Buried Contact (BC) that connects a storage electrode of a capacitor with a drain region of the transistor and a bit line.
In order to provide adequate spacing margins, the unit cell structure is changing from a symmetrical unit cell structure, such as a conventional dog-bone shape, to an asymmetrical unit cell structure. For example, a "T"-type active pattern has now been used for more than three generations of 16 MB DRAM.
As is well known to those having skill in the art, integrated circuit memory devices generally include an array of sub-blocks in an integrated circuit. For example, multiple rows and multiple columns of sub-blocks may be provided. Each of the sub-blocks includes an array of unit cells therein. The unit cells generally include one to four or more memory cells that are addressable by row and by column. The orientation of the unit cells of a sub-block generally define an orientation direction of the sub-block.
Generally, all of the patterns of the sub-blocks are not unidirectional when the memory cell array in a DRAM chip is planned or laid out. For example, half of the integrated circuit may be laid out, and the remaining half is laid out by reflecting the previously laid out part about a horizontal or vertical axis, to provide sub-blocks that are mirror images of one another.
As a specific example, for a 16 MB DRAM that uses a T-type active area pattern, the entire integrated circuit may be divided into four 4 MB sub-blocks. One sub-block is laid out, and this sub-block is reflected about horizontal and vertical axes passing through the center of the integrated circuit, to produce the four sub-blocks that are mirror images of one another. Thus, for a 16 MB DRAM, the upper 8 MB sub- blocks are symmetrical to the lower 8 MB sub-blocks with respect to a row decoder.
In fabricating such memory devices, many variables may affect the spacing margins during fabrication. The margins may vary from one array of sub-blocks to another array of sub-blocks. Accordingly, to preserve the margins above a required minimum, the management of the margin of each individual process must generally be tightly controlled.
The characteristics of the respective sub-blocks, including the spacing margins therein, are closely related to various fabrication processes, such as photolithography, etching, deposition, ion implantation and diffusion. Although the characteristics of the sub-blocks can be measured after fabricating the integrated circuit, it is difficult to predict the changes that misalignments will have on the integrated circuit itself prior to fabrication. Also, if a process variable is controlled in order to increase spacing margins, and thereby reduce potential defects, defects may occur in another sub-block as a result of the control.